The present invention, in general, relates to integrated semi-conductor circuits. More specifically, the present invention is directed to an integrated semi-conductor circuit comprising a substrate composed of silicon in/on which the elements defining the circuits are generated. The circuit comprises at least two metallization levels composed of aluminum or aluminum compounds that are separated by an insulating layer. The metallization levels are connected to one another, and to the regions in/on the silicon substrate to be contacted, by use of metal silicide intermediate layers and via hole fillers composed of tungsten.
Structures in the range of 1 um and below are known and utilized in the progressive miniaturization of semi-conductor components. In order to be able to electrically drive the resultant extremely small, active regions on the semi-conductor substrate, it is necessary to use metallic interconnects. The interconnects are separated from the semi-conductor substrate by an insulating layer, composed of for example SiO.sub.2, so that contact only occurs at defined locations. The connection to the active regions of the semi-conductor substrate ensues via contact holes which are etched into the insulating layer.
VLSI semi-conductor circuits are similar in construction wherein two or more interconnect levels are required for the electrical supply of the extremely densely packed, active regions. Likewise, the electrical contact between the various interconnect levels must be produced utilizing very small holes (referred to as via holes).
Since the insulating layer must comprise a minimum thickness of approximately 0.7 to about 1.5 um due to circuit-oriented reasons (for example, parasitic capacitances), depth-to-diameter ratios of greater than or equal to one occur at the contact holes or, respectively, via holes. Given these extremely small and deep via holes, the layer thickness of the interconnects at the sidewalls of the contact hole decreases greatly (approximately a 55 to about 80% decrease) when the interconnect material, for example aluminum alloys such as aluminum-silicon (1%), are applied by cathode sputtering as heretofore was standard. Since the interconnects have extremely high current densities (for example, 1.times.10.sup.6 A/cm.sup.2), every cross-sectional constriction effects a local temperature rise that accelerates an undesired material transport (diffusion, reaction) at the boundary surfaces between the various materials. This local temperature rise can also lead to the burn-through of an interconnect.
A further problem that is encountered with these miniaturized semi-conductor components is that cavities can form in the via holes after the coating with, for example, aluminum-silicon. When an insulating layer is subsequently deposited thereon, for example as a foundation for a further aluminum-silicon interconnect level, then it is almost impossible to completely fill out the cavity situated in the via hole. Because reactive and/or corrosive agents can collect in this cavity during further manufacturing steps, it is necessary for reliable components to specify a contact hole or, respectively, via hole metallization pattern wherein a complete filling is achieved.
The art has developed methods that meet some of the individual requirements set forth above. The critical problem to be overcome is filling up the contact holes and providing a suitable connection to the metallization levels.
European patent application No. 86 11 00 76.6, for example, proposes that contact holes in the insulating layers, or what are referred to as via holes to more deeply placed metallization levels, be completely filled without cavities with electrically conductive material by first coating surface-wide with a metal silicide by deposition from the vapor phase. The silicide layer is then, in turn, removed again on the horizontal surface of the silicon substrate, and the contact hole is subsequently filled with metallically conductive material by selective deposition from the vapor phase. Refractory metals and their silicides are thereby employed.
A similar via hole filling method is proposed in European patent application No. 86 10 28 21.5, whereby aluminum is employed instead of the silicides and refractory metals. The aluminum is deposited surface-wide by low-pressure chemical vapor deposition (LPCVD) and is etched back to the height of the via hole.
European patent application No. P 36 15 893.3 discloses an integrated semi-conductor circuit comprising an outer interconnect level composed of aluminum or an aluminum alloy. A metal silicide intermediate layer of tantalum di-silicide is deposited for improving the current load in the via hole.
German patent application No. P 36 15 893.3 discloses the utilization of tungsten for filling via holes in the insulating layers of the integrated semi-conductor circuits. Due to the good edge coverage achieved by the CVD method, the layer grows in the via hole with roughly the same speed from all sides and fills the via hole.